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KB3920
Keyboard Controller
Datasheet
Revision 0.8
Jun. 2006
ENE RESERVES THE RIGHT TO AMEND THIS DOCUMENT WITHOUT NOTICE AT ANY TIME. ENE
ASSUMES NO RESPONSIBILITY FOR ANY ERRORS APPEAR IN THE DOCUMENT, AND ENE DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF ENE PRODUCTS
INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, OR
INFRINGEMENT OF ANY PATENTS, COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
Headquarters
4F-1, No.9, Prosperity Rd.,
Science-based Industrial Park,
Hsinchu City, Taiwan, R.O.C
TEL: 886-3-6662888
FAX: 886-3-6662999
http://www.ene.com.tw
Taipei Office
9F, No.88, Bauchiau Rd.
Shindian City, Taipei,
Taiwan, R.O.C.
TEL: 886-2-89111525
FAX: 886-2-89111523
Copyright©2006, ENE Technology Inc. All rights reserved.
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KB3920 Keyboard Controller Datasheet
CONTENT
1. FEATURES ...............................................................................................................4
1.1 FEATURE SUMMARY ........................................................................................................... 4
1.2 COMPARISON ON KB3910 176-PIN VS. KB3920 144-PIN ...................................................... 7
1.3 BLOCK DIAGRAM ............................................................................................................... 8
2. PIN ASSIGNMENT AND DESCRIPTION .............................................................9
2.1 144 PIN LQFP DIAGRAM TOP VIEW ..................................................................................... 9
2.2 169 GBA DIAGRAM TOP VIEW .......................................................................................... 10
2.3 PIN ASSIGNMENT SIDE A .................................................................................................. 12
2.4 PIN ASSIGNMENT SIDE B .................................................................................................. 12
2.5 PIN ASSIGNMENT SIDE C .................................................................................................. 13
2.6 PIN ASSIGNMENT SIDE D .................................................................................................. 14
2.7 I/O CELL DESCRIPTIONS ................................................................................................... 15
2.7.1 I/O Buffer Table .......................................................................................................... 15
2.7.2 I/O Buffer Characteristic Table.................................................................................... 15
2.7.3 I/O Buffer Naming Convention .................................................................................... 15
3. PIN DESCRIPTIONS............................................................................................. 16
3.1 HARDWARE STRAP .......................................................................................................... 16
3.2 PIN DESCRIPTIONS BY FUNCTIONALITY............................................................................... 16
3.2.1 Low Pin Count Interface Pin Descriptions................................................................... 16
3.2.2 X-BUS Interface Pin Descriptions ............................................................................... 16
3.2.3 PS2 Interface Pin Descriptions.................................................................................... 17
3.2.4 Internal Keyboard Encoder Pin Descriptions............................................................... 17
3.2.5 SMBus Pin Descriptions.............................................................................................. 17
3.2.6 FAN Pin Descriptions.................................................................................................. 17
3.2.7 Pulse Width Modulation Pin Descriptions.................................................................... 17
3.2.8 Analog to Digital Pin Descriptions .............................................................................. 17
3.2.9 Digital to Analog Pin Descriptions .............................................................................. 18
3.2.10 8051 External Interface Pin Descriptions .................................................................. 18
3.2.11 Clock Pin Descriptions .............................................................................................. 18
3.2.12 Miscellaneous Pin Descriptions................................................................................. 18
3.2.13 Power Pin Descriptions............................................................................................. 19
4. MODULE DESCRIPTIONS .................................................................................. 19
4.1 CHIP ARCHITECTURE ........................................................................................................ 19
Copyright©2006, ENE Technology Inc.
1
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KB3920 Keyboard Controller Datasheet
4.1.1 Power Planes.............................................................................................................. 19
4.1.2 Clock Domains............................................................................................................ 19
4.1.3 Reset Domains ............................................................................................................ 19
4.1.4 Internal Memory Map ................................................................................................. 19
4.2 GPIO ............................................................................................................................. 20
4.2.1 GPIO Functional Description...................................................................................... 20
4.2.2 GPIO Input / Output Control Structure ........................................................................ 22
4.2.3 GPIO Registers Descriptions....................................................................................... 24
4.3 KBC .............................................................................................................................. 35
4.3.1 KBC Functional Description ....................................................................................... 36
4.3.2 KBC Registers Descriptions ........................................................................................ 37
4.4 IKB ................................................................................................................................ 38
4.4.1 IKB Functional Description......................................................................................... 38
4.4.2 IKB Registers Descriptions.......................................................................................... 39
4.5 PWM ............................................................................................................................. 42
4.5.1 PWM Functional Description...................................................................................... 42
4.5.2 PWM Registers Descriptions ....................................................................................... 42
4.6 FAN ................................................................................................................................ 43
4.6.1 FAN Functional Description........................................................................................ 43
4.6.2 Functions in a FAN controller: .................................................................................... 43
4.6.3 FAN Tachometer Monitor ............................................................................................ 43
4.6.4 FAN PWM Control ...................................................................................................... 43
4.6.5 FAN Registers Descriptions......................................................................................... 44
4.7 GPT............................................................................................................................... 45
4.7.1 GPT Functional Description........................................................................................ 45
4.7.2 GPT Register Descriptions .......................................................................................... 45
4.8 SPI DEVICE I NTERFACE .................................................................................................... 46
4.8.1 SDI Functional Description......................................................................................... 46
4.8.2 SDI Registers Descriptions.......................................................................................... 46
4.9 WDT .............................................................................................................................. 47
4.9.1 WDT Functional Description....................................................................................... 47
4.9.2 WDT Registers Descriptions (Base address = FE80h, 16 bytes) ................................... 47
4.10 LPC ............................................................................................................................. 48